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A report by Divyansh Agrawal describes Qwenputer, an experimental version of Qwen3.5 4B with a compiled RISC-V CPU operating inside the model’s forward passes. The creator says it passes official RISC-V tests and ran 18 million instructions without error; those results are reported by the creator, not independently verified in the supplied material.
Developer Divyansh Agrawal has reported building Qwenputer, an experimental version of Qwen3.5 4B with a 32-bit RISC-V CPU compiled into the model’s weights and using its Gated DeltaNet state as RAM. The CPU runs through the model’s forward passes rather than an external execution tool; Agrawal says it passes official RISC-V tests and completed an 18-million-instruction run without an error.
Agrawal describes Qwenputer as a stock Qwen3.5 4B model with computer circuitry added to its weights. The CPU is an RV32IM core, with the Zba extension and a small unit for larger-number arithmetic. It occupies 11 layers placed before Qwen’s original 32 layers. According to the report, the added computer weights do not alter the original Qwen weights.
The design uses the model’s Gated DeltaNet (GDN) state as addressable memory. Agrawal says setting the gate to one prevents stored values from fading, while a write strength of one and one-hot keys allow a write to replace a selected row and a query to retrieve it. A compiler maps CPU operations into model components: attention heads access memory, feed-forward units perform arithmetic, and DeltaNet heads retain state.
During execution, instructions are represented in generated tokens that carry an address, a value and a step marker. Agrawal says the CPU passes the official riscv-tests, produces results matching QEMU, and ran 18 million instructions in a free-running test. The report also says it can run C and MicroPython programs, though slowly. These are the creator’s reported results; the source material does not provide an independent evaluation.
A CPU Runs Inside Model State
Qwenputer offers a concrete demonstration of a model’s internal recurrent state being used not just to retain conversational information, but as exact, addressable computer memory. If the reported behavior holds under independent testing, the experiment could help researchers explore how learned-model architectures can host deterministic computation alongside language generation.
The distinction from conventional tool use is central. Agrawal says the CPU executes within the model’s forward passes and does not depend on an external runtime or tool call. That does not mean Qwenputer is a general-purpose computer: its reported CPU is a limited 32-bit core, and its programming performance is described as slow. The result is best understood as a research demonstration, not a replacement for physical processors or software environments.
The approach may also interest researchers studying model monitoring and internal reasoning. Agrawal points to follow-up work on hiding reasoning in recurrent state and using compiled weights for monitoring. Those are related research questions, not findings established by the CPU demonstration itself.
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DeltaNet State Becomes Addressable
Qwen3.5 uses a hybrid architecture. In Agrawal’s description, three out of every four attention layers use Gated DeltaNet, a form of linear recurrent network whose heads maintain state matrices. The gates ordinarily control forgetting, and updates modify the stored state as tokens are processed. Qwenputer configures those mechanisms to act more like memory cells.
The underlying idea of delta-rule linear attention as associative memory predates this project. Agrawal cites a 2021 paper by Imanol Schlag, Kazuki Irie and Jürgen Schmidhuber on linear transformers as “fast weight programmers.” The report’s claimed advance is making that state exact and addressable enough to support a CPU in a production model’s architecture. Agrawal says no additional training is required: a compiler assigns the computer’s weights.
The creator says Qwenputer and its code are available through Hugging Face, ModelScope and GitHub. A small driver, RvChat, loads firmware into the GDN state and keeps the CPU’s execution trace out of Qwen’s own layers, according to the report.
“The CPU runs completely within the forward passes of the model.”
— Divyansh Agrawal, Qwenputer’s creator
Independent Testing Remains Open
The performance and reliability figures in the source are claims by the project’s creator. The supplied material does not include independent test results, external replication, or detailed benchmark procedures for the 18-million-instruction run. It also does not provide enough information to compare execution speed, energy use or memory capacity with conventional processors or other model-based computation.
The report characterizes the implementation as deterministic, but the material provided does not spell out the precise test conditions or how deterministic behavior was measured across repeated runs. The CPU’s slow performance on C and MicroPython is acknowledged, while the size of programs it can handle and the limits of its experimental file storage are not specified here. Those details would help establish how broadly the system can be used beyond demonstration programs.
Code Offers a Replication Path
Agrawal says the model is available on Hugging Face and ModelScope, with code on GitHub, giving other researchers a way to inspect the implementation and attempt to reproduce the tests. The next useful evidence would include independent runs of the RISC-V test suite, repeated free-running instruction tests, and published details on speed and supported program sizes.
No further testing schedule or external validation is specified in the source material. Until such evidence is available, Qwenputer’s reported CPU capabilities should be treated as an experimental demonstration, with its performance claims attributed to its creator.
Key Questions
What is Qwenputer?
Qwenputer is an experimental version of Qwen3.5 4B with a RISC-V CPU compiled into its model weights, according to its creator, Divyansh Agrawal.
Does it use an external code execution tool?
Agrawal says the CPU runs inside the model’s forward passes, without an external runtime or tool call. A driver loads firmware into the model state, according to the report.
How does the model provide memory for the CPU?
The project uses Gated DeltaNet state as addressable memory. Agrawal says its configuration lets the system write values to selected rows and retrieve them with one-hot queries.
Has the CPU’s performance been independently verified?
The source material reports that it passes official RISC-V tests, matches QEMU and ran 18 million instructions without error, but these results are attributed to Agrawal. Independent verification is not included in the material.
Can Qwenputer run ordinary software?
Agrawal says it can run C and MicroPython programs, though slowly. The report describes a 32-bit CPU and says it is not a Linux-class system; it does not establish broader software compatibility.
Source: divagr.com
